1. Field of the Invention
The present invention relates to processing signal data and in particular relates to correcting clock phase offset while processing signal data.
2. Description of the Prior Art
Clock path delay mismatch or clock phase offset is an important parameter in signal data processing and consequently in the design of signal data processors. As signal data processors become ever smaller (due to process shrinking) and more complex, this parameter becomes a more significant problem faced by the designers of such signal data processors.
There are various reasons for the increasing significance of clock phase offset. Firstly as complementary metal-oxide-semiconductor (CMOS) minimum feature sizes become smaller, the mismatch between different clock buffers or different clock paths increases dramatically. It is known in the art that offset voltage is dependent upon the threshold voltage (Vt) mismatch and β mismatch. Although β mismatch contributes more with smaller feature sizes, in current mainstream CMOS technology, the Vt mismatch is the dominant factor. The Vt offset (Vos) can be calculated as the following equation:
      Vos    ⁢          ❘      rms        =      Av          nwl      where Vos is the RMS offset voltage,
Av is a process parameter,
n is the finger number, and
w and l are the MOSFET width and length respectively.
Although Av is improved slightly, in order to take advantage of the advanced CMOS technology, Vos is still increasing due to smaller MOSFET size. For each buffer stage, the delay mismatch (ΔTd) can be calculated as the following equation:
      Δ    ⁢                  ⁢    Td    =      Vos    SR  where SR is the clock slew rate.
Assuming same clock rate and same slew rate design, ΔTd is proportional to Vos as shown in FIG. 1. In this figure, threshold 1 is the switch point of a first clock buffer 1 and threshold 2 is the switch point of a second clock buffer 2. Threshold 1=threshold 2+Vos due to the mismatch.
Secondly, due to the increased complexity of mixed signal circuit (high speed PHY) designs, clock distribution becomes more involved. Clocks need more buffers or more complicated clock trees to be delivered to their destinations, which increases the clock delay mismatch significantly.
Thirdly, higher data and clock rates make the situation even worse even with the same ΔTd design. The phase offset is proportional to the data rate, thus worsening as data rates increase.
According to the prior art the clock phase offset is corrected for in an initial calibration phase, e.g. during power up reset. This initial calibration can correct most of the clock phase offset. The present techniques recognise that later-arising temperature and/or power supply (e.g. low frequency power supply noise) induced offset can cause further offset to be introduced. Such factors become more significant as geometries decrease and may cause the clock offset to vary. Such dynamic variation in the clock offset can lead to levels of jitter that are problematic when signal data processing.
FIG. 2 schematically illustrates an arrangement for the generation of two clock signals in a receiver aligned with a received data stream in the prior art. A voltage controlled oscillator (VCO) 10 generates a single frequency clock locked to a reference clock. I/Q clock generation block 20 creates two clock signals (I clock and Q clock) with a 90 degree offset from one another. In order to align these clocks with the received data stream, each of the I/Q clocks is then passed to two phase interpolators (PIs) 30 and 40. Phase interpolators 30 and 40 are controlled by the digital vector ctrl which is determined by the clock data recovery performed by clock data recovery unit 50 on the received data stream. Phase interpolators 30 and 40 then generate two new clocks iclk and qclk with 90 degree offset from one another, as well as aligned with the incoming data. The iclk and qclk clocks are then used to sample and recover the incoming signal data received by the apparatus. The calibration of this arrangement is provided by delay units 60 and 70, the control values of which are set in registers R1 and R2 at an initial calibration phase prior to processing data.
A data receiver may alternatively generate iclk and qclk aligned with a stream of received data by means of phase locked loop (PLL) based clock generation. An example arrangement is schematically illustrated in FIG. 3. Here a phase detector 100 receives the incoming data stream and passes phase information via a loop filter 110 to voltage controlled oscillator (VCO) 120. The VCO provides a reference signal to I/Q clock generator 130 which generates iclk and qclk. The iclk and qclk are fed back to phase detector 100, so that the loop is locked and so that iclk and qclk are aligned with the stream of received data. This arrangement could also be calibrated by delay units (not illustrated) at an initial calibration phase as discussed with reference to FIG. 2.
Returning to the example arrangement of FIG. 2, the phase interpolators, although perhaps initially calibrated by the delay units following them within the required tolerances, are recognised by the present techniques to suffer from various further impairments such as delay mismatch and integral non-linearity (INL). Because of this iclk and qclk not only suffer from static clock offset (e.g delay mismatch), but may also suffer from dynamically evolving clock offsets (e.g due to INL, temperature dependent delay mismatch or power supply dependent mismatch). The latter dynamic clock offsets are not addressed by power up reset or initial calibration, and as application speeds increase and process geometries decrease dynamic offset becomes one of the most significant limiting factors on coping with variations in clock phase offsets.
It is thus desirable to provide a method of processing signal data in which this dynamically arising clock offset is addressed.